The present invention relates to a small area and low current drain frequency divider cell for Integrated Circuits.
As is known, electric low frequency signals are usually generated through the use of very high RC time constants, which are very difficult to be obtained in IC's, in which large capacity and/or resistance values are not feasible. Thus, when a low frequency signal is required in an IC, it is preferred to generate a higher frequency signal and then reduce its frequency by means of a divider comprising a plurality of cascade coupled master-slave flip-flop cells, each of which provides a division by two.
Each of the divider cells typically comprises, in addition to several transistors, also several resistors and, accordingly, each cell will occupy a comparatively large area. Moreover, because of the mentioned difficulty of providing high resistance values, the cell will also absorb a rather high current.
Since a frequency reduction of one order of magnitude requires a divider with three or four flip-flop cells, the above problem is very serious.